Some conferences are exciting, and others are less so; this year’s ISSCC fell somewhere in-between. The plenary sessions was more interesting than usual, with Jeff Hawkins’s presentation regarding the question as to why computers can’t be more brain like, going over very well with the attendees. If you have not read Jeff’s book titled On Intelligence, you ought to give it a look. His theory regarding hierarchical temporal memory is very interesting and just might inspire people to come up with new approaches to computing in the future.

On the technical side of things, this year’s memory forum focused on embedded memories. For example, engineers from TI do not think that embedded memories such as eDRAM make sense for mobile processors at the moment since capacity wise the cross-over point for eDRAM to become cost-efficient is beyond what mobile processors require at present. On the other hand, given IBM’s need for large caches on some of their processors, it should be of no surprise that they were significantly more upbeat on embedded memory technology. The most interesting slides from a pure technical perspective though were presented by Hiroyuki Yamauchi from the Fukuoka Institute of Technology, in which he depicted SRAM design and scaling limitations in a myriad of graphs. He offered enough data to give one a headache but one thing was clear, the regular six transistor (6T) SRAM memory cell won’t scale, even when combined with other circuit tricks. Tom Andre from Freescale also gave a nice presentation regarding MRAM. If you ever need to understand how a write is performed in a Toggle MRAM send him a note requesting his slides.

The microprocessor session was somewhat exciting mainly because Sun made some interesting architectural decisions for their latest SPARC processor, such as sharing instruction/data caches and ALUs between several cores, implementing the scout-thread model and enabling transactional memory support. Tilera’s presentation was a yawn at best, and featured not much in terms of new content regarding their Tile64 processor, other than an explanation of all the networking protocols that the on-chip network supports. Intel’s 2-Billion Transistor chip featured some interesting soft-error-rate (SER) hardened latches and register files. While they are larger than usual cells, they are significantly easier to implement than ECC for example.

One of the more entertaining evening sessions proved to be the fight them or invite them panel discussion regarding private equity. The panel agreed that private equity probably underestimated the volatility of the semiconductor industry and that the two major experiments last year that featured Freescale and FXP, might have scared private equity firms away from semiconductor companies for now. Straying from the main topic, the discussion also revealed some statistics that ought to be a cause for concern. For example, while in 2007 the amount of venture capital raised by startups has been the highest in six years, the amount of funding for semiconductor companies has actually been decreasing over the last few years. The panel of experts did not have a clear opinion as to why this was the case, other than suspecting that VCs might have found more lucrative opportunities. Additional topics discussed during the session included: the United States being overly capitalistic, the implications of the mortgage and housing crisis on the semiconductor economy, and the decrease of Japan’s market share as a semiconductor supplier over the last few decades. As stated before, it was a very entertaining session.