On the mobile side of things Intel presented a processor targeted at ultra mobile applications capable of running at up to 2GHz - not bad for a sub 2W part. Intel highlighted the fact that their power analysis showed that a simple in-order multi-threaded machine was the best option for low-power applications. Additionally, the core also featured a special array for processor state preservation while the core was in sleep mode, thus allowing for quick wake-up times. Not to be outdone, TI presented an SOC that had everything but kitchen-sink on it, including an ARM core, a DSP chip, and an imager processor. The TI core utilized extensive body-biasing including forward body -biasing for cold-devices and reverse body-biasing for hot deices. The biasing was combined with specific power-states to obtain maximum performance or power savings.

The SRAM session also featured several interesting papers and once again body-biasing was used extensively. Intel, in addition to an op-amp based active feedback sleep scheme, utilized forward body-biasing on pmos devices in their 6T bit-cells to improve low-voltage operation of their arrays. Renesas on the other hand utilized reverse body-biasing on their nmos and pmos devices in conjunction with threshold monitoring to reduce mismatch between devices and thus improving the operating margins of their SRAMs. IBM presented a two-stage sense amplifier that significantly reduced power since it reduced the voltage swing on their global data lines. Their array also featured an embedded trench capacitor which stores enough charge to allow the array to exit from retention-mode with no cycle penalty. Kawasaki presented an asymmetric 6T cell, which featured very good static noise margin and write margin numbers - their numbers seemed almost too good to be true, but the presenter argued that the larger devices compensated for the asymmetric distortion. MIT presented a quite interesting single-ended non-strobed sense-amp (NSR-SA), which seems to have better mean and sigma variation than conventional differential sense-amplifiers. It requires several ratioed circuits and also incurs a power penalty due to crowbar currents, but is interesting nevertheless. Finally, just like every year a 10T sub-threshold bit-cell was presented for ultra low-power designs, this year by Purdue and IBM.