Technical Bits

Last year we wrote about ionic wind engine research that was conducted at Purdue University and allowed the team to increase the heat-transfer coefficient of a regular fan by 250 percent, thus significantly improving the cooling solution. Since then chips have definitely not become any cooler. The power envelope for individual cores might have decreased due to the re-emergence of simpler architectures with shallower pipelines, but with chip companies squeezing ever more cores into smaller packages, the heat problem is not going away any time soon. To compound the problem, keep in mind that for all these cores to perform useful work, they need to constantly be supplied with data, which leads to more I/O circuitry. The I/O circuitry in turn often times consists of many analog blocks that generally don’t scale very well with voltage, leading to more heat.

But rest assured, where there are interesting problems to be sovled, smart minds somewhere are working on doing just that. As happens to be the case, once again researchers at Purdue University have developed a technology that through the use of microjets enables them to deposit liquid into tiny channels on the chip surface resulting in a high-performance cooling solution. Conventional chips generate about 100 watts per square centimeter and can be air cooled via heat sinks and fans. Liquid cooling solutions are generally limited to about 200 watts per square centimeter. The Purdue team claims that their new cooling technology will allow chips with a power density of up to 1,000 watts per square centimeter. The key for achieving this type of cooling is a non-conductive liquid called hydrofluorocarbon. This fluid is pumped into the tiny channels on the chip surface via microjets through holes in the metal plate that sits on top of the channels. As the liquid circulates through the channels, it heats up until it momentarily becomes a vapor, which significantly enhances the cooling process. The micorjets ensure that the fluid is evenly distributed along the channels. This avoids the previous pitfall of fluids traversing chips from one side to the other, heating up along the way and thus losing their cooling ability.

Of course, the question has to be asked whether it will be possible to commercialize this technology. In specific niches, such as super-computing, where cost usually takes a backseat to performance, this cooling solution might indeed be acceptable. However, unless the technology can be made affordable enough so that major chip vendors can incorporate it into their products without alienating their consumers, it will likely fall by the wayside. I don’t have any chip packaging background and as such estimating the costs of this approach in its present form are beyond me, however, something tells me that they are not insignificant.

A little over a year ago we briefly discussed through-silicon vias (TSV). We examined some potential advantages and provided a link to a little TSV primer. Back then, the projection was that we ought to expect chips featuring TSV by the beginning of 2008. And while a few ICs here and there have been manufactured using TSV, a general standard was lacking thus slowing adoption across the industry. To overcome this problem, the 3D-IC Alliance, whose founding members include Tezzaron Semiconductor and Ziptronix, has released a first standard for 3D integration, dubbed the Intimate Memory Interface Standard (IMIS) – could they really not come up with a better name? While complaining, what is up with the 3D-IC website? It is truly an eyesore, and bags for a makeover.

Anyhow, as with most standards, the specification is quite extensive coming in at over thirty pages, but keep in mind that tables and diagrams take up a lot of that space.  The contents cover pin specifications and pin usage direction for most common memory types and their variations. Following the pins, the actual surface and target requirements are discussed at length. This section is split into three categories: Direct Bond Interconnect (DBI) which is championed by Ziptronix, Copper to Copper Bonding which is backed by Tezzaron under the FaStack brand, and a third category which at this point is undefined and reserved for future use. The final section is a short discussion of footprint diagrams and their variations.

As mentioned in our prior post, there are some immediate advantages that come to mind: shorter interconnect paths and more compact floor plans that no longer need to account for large caches, however, what we missed are the possible implications for Integrated Circuit (IC) security. On this topic, Tezzaron has a short paper which within the space of a couple pages, discusses on a high-level some of the reverse engineering techniques, as well as the two major security advantages for 3D ICs. To summarize, the first advantage is that if one of the layers in the stack is face-up while the connecting one is face-down, the outside surfaces would consist only of I/O pads, making etching and de-layering difficult. The second advantage is the fact that with a well defined interface, separate components can now be manufactured at different foundries, further reducing the risk that the final functionality of the part might be exposed. Obviously, the paper is intended as promotional material for 3D ICs, nevertheless it makes a few interesting points and is worth checking out for those interested in the subject.

Having covered magnetoresistive random access memory (MRAM) on several occasions it is time to move on to something a little bit more exotic, namely nanotubes. The January issue of the Nature Nanotechnology Magazine contains a very interesting article titled: Nanoscale Memory Cell based on a Nanoelectromechanical Switched Capacitor. Unfortunately, unless you are a subscriber to the magazine or might have access to it through your company, you will not be able to access the full article. Thankfully, nanowerk.com has a pretty nice write-up on the article and even obtained permission to reprint several of the illustrations. Looking at these illustrations, it can be seen that the proposed device is a three terminal device consisting of a source, drain, and gate. The source and drain both contain vertical multiwalled carbon nanotubes (MWCNT). The nanotube on the source, which is grounded, is covered with a dielectric layer which in turn is covered with a metal layer, thus completing the capacitor. The drain terminal is connected to what in a conventional design would be a bit-line and the gate terminal is connected to what would be a word-line. The mechanical switching occurs when bias voltages are applied to the drain and gate terminals. That is, when a gate voltage is applied but no drain voltage is applied, nothing happens. However, when both drain and gate voltages are applied, such that the gate voltage is higher than the drain voltage, the nanotube on the drain is subject to a repulsive electrostatic force from the gate and bends towards the source. If it bends far enough it establishes contact with the metal layer of the source and charges the capacitor effectively storing a logical one in the bit-cell, hence the name nanoelectromechanical switched capacitor (NEM).

The authors of this paper have only implemented the writing portion so far, but according to the paper, reading from the bit-cell would follow a similar sequence with the exception that the nanotube on the drain would be unable to make contact with a bit-cell that contained a logical one since even though it would still experience an electrostatic force from the gate, it would also be subject to a counter force from the charged capacitor, and thus no current would flow from the capacitor to any current sensing circuitry. All of the above is just a brief summary, the article contains all the dimensions used for constructing the device, a detailed description of the manufacturing method, all the voltages and capacitance numbers, and of course a few equations for calculating the switching speeds and effective capacitances, and is therefore definitely worth a look if you have access to it. While all of this is very preliminary work, it is nevertheless very fascinating and only gives us a small glimpse of all the esoteric structures that circuit designers might get to play with in the coming years.