A little over a year ago we briefly discussed through-silicon vias (TSV). We examined some potential advantages and provided a link to a little TSV primer. Back then, the projection was that we ought to expect chips featuring TSV by the beginning of 2008. And while a few ICs here and there have been manufactured using TSV, a general standard was lacking thus slowing adoption across the industry. To overcome this problem, the 3D-IC Alliance, whose founding members include Tezzaron Semiconductor and Ziptronix, has released a first standard for 3D integration, dubbed the Intimate Memory Interface Standard (IMIS) – could they really not come up with a better name? While complaining, what is up with the 3D-IC website? It is truly an eyesore, and bags for a makeover.

Anyhow, as with most standards, the specification is quite extensive coming in at over thirty pages, but keep in mind that tables and diagrams take up a lot of that space.  The contents cover pin specifications and pin usage direction for most common memory types and their variations. Following the pins, the actual surface and target requirements are discussed at length. This section is split into three categories: Direct Bond Interconnect (DBI) which is championed by Ziptronix, Copper to Copper Bonding which is backed by Tezzaron under the FaStack brand, and a third category which at this point is undefined and reserved for future use. The final section is a short discussion of footprint diagrams and their variations.

As mentioned in our prior post, there are some immediate advantages that come to mind: shorter interconnect paths and more compact floor plans that no longer need to account for large caches, however, what we missed are the possible implications for Integrated Circuit (IC) security. On this topic, Tezzaron has a short paper which within the space of a couple pages, discusses on a high-level some of the reverse engineering techniques, as well as the two major security advantages for 3D ICs. To summarize, the first advantage is that if one of the layers in the stack is face-up while the connecting one is face-down, the outside surfaces would consist only of I/O pads, making etching and de-layering difficult. The second advantage is the fact that with a well defined interface, separate components can now be manufactured at different foundries, further reducing the risk that the final functionality of the part might be exposed. Obviously, the paper is intended as promotional material for 3D ICs, nevertheless it makes a few interesting points and is worth checking out for those interested in the subject.