On the mobile side of things Intel presented a processor targeted at ultra mobile applications capable of running at up to 2GHz - not bad for a sub 2W part. Intel highlighted the fact that their power analysis showed that a simple in-order multi-threaded machine was the best option for low-power applications. Additionally, the core also featured a special array for processor state preservation while the core was in sleep mode, thus allowing for quick wake-up times. Not to be outdone, TI presented an SOC that had everything but kitchen-sink on it, including an ARM core, a DSP chip, and an imager processor. The TI core utilized extensive body-biasing including forward body -biasing for cold-devices and reverse body-biasing for hot deices. The biasing was combined with specific power-states to obtain maximum performance or power savings.

The SRAM session also featured several interesting papers and once again body-biasing was used extensively. Intel, in addition to an op-amp based active feedback sleep scheme, utilized forward body-biasing on pmos devices in their 6T bit-cells to improve low-voltage operation of their arrays. Renesas on the other hand utilized reverse body-biasing on their nmos and pmos devices in conjunction with threshold monitoring to reduce mismatch between devices and thus improving the operating margins of their SRAMs. IBM presented a two-stage sense amplifier that significantly reduced power since it reduced the voltage swing on their global data lines. Their array also featured an embedded trench capacitor which stores enough charge to allow the array to exit from retention-mode with no cycle penalty. Kawasaki presented an asymmetric 6T cell, which featured very good static noise margin and write margin numbers - their numbers seemed almost too good to be true, but the presenter argued that the larger devices compensated for the asymmetric distortion. MIT presented a quite interesting single-ended non-strobed sense-amp (NSR-SA), which seems to have better mean and sigma variation than conventional differential sense-amplifiers. It requires several ratioed circuits and also incurs a power penalty due to crowbar currents, but is interesting nevertheless. Finally, just like every year a 10T sub-threshold bit-cell was presented for ultra low-power designs, this year by Purdue and IBM.

Some conferences are exciting, and others are less so; this year’s ISSCC fell somewhere in-between. The plenary sessions was more interesting than usual, with Jeff Hawkins’s presentation regarding the question as to why computers can’t be more brain like, going over very well with the attendees. If you have not read Jeff’s book titled On Intelligence, you ought to give it a look. His theory regarding hierarchical temporal memory is very interesting and just might inspire people to come up with new approaches to computing in the future.

On the technical side of things, this year’s memory forum focused on embedded memories. For example, engineers from TI do not think that embedded memories such as eDRAM make sense for mobile processors at the moment since capacity wise the cross-over point for eDRAM to become cost-efficient is beyond what mobile processors require at present. On the other hand, given IBM’s need for large caches on some of their processors, it should be of no surprise that they were significantly more upbeat on embedded memory technology. The most interesting slides from a pure technical perspective though were presented by Hiroyuki Yamauchi from the Fukuoka Institute of Technology, in which he depicted SRAM design and scaling limitations in a myriad of graphs. He offered enough data to give one a headache but one thing was clear, the regular six transistor (6T) SRAM memory cell won’t scale, even when combined with other circuit tricks. Tom Andre from Freescale also gave a nice presentation regarding MRAM. If you ever need to understand how a write is performed in a Toggle MRAM send him a note requesting his slides.

The microprocessor session was somewhat exciting mainly because Sun made some interesting architectural decisions for their latest SPARC processor, such as sharing instruction/data caches and ALUs between several cores, implementing the scout-thread model and enabling transactional memory support. Tilera’s presentation was a yawn at best, and featured not much in terms of new content regarding their Tile64 processor, other than an explanation of all the networking protocols that the on-chip network supports. Intel’s 2-Billion Transistor chip featured some interesting soft-error-rate (SER) hardened latches and register files. While they are larger than usual cells, they are significantly easier to implement than ECC for example.

One of the more entertaining evening sessions proved to be the fight them or invite them panel discussion regarding private equity. The panel agreed that private equity probably underestimated the volatility of the semiconductor industry and that the two major experiments last year that featured Freescale and FXP, might have scared private equity firms away from semiconductor companies for now. Straying from the main topic, the discussion also revealed some statistics that ought to be a cause for concern. For example, while in 2007 the amount of venture capital raised by startups has been the highest in six years, the amount of funding for semiconductor companies has actually been decreasing over the last few years. The panel of experts did not have a clear opinion as to why this was the case, other than suspecting that VCs might have found more lucrative opportunities. Additional topics discussed during the session included: the United States being overly capitalistic, the implications of the mortgage and housing crisis on the semiconductor economy, and the decrease of Japan’s market share as a semiconductor supplier over the last few decades. As stated before, it was a very entertaining session.

Many companies have promised to take on Intel in the x86 space, but not many have fared very well, either going under or being scooped up Intel’s arch rival AMD. Today, News.com posted an interesting article about a Santa Clara, California based startup named Montalvo Systems that is supposedly designing multi-core chips for the ultraportable and notebook spaces. Don’t bother checking their web site-unless you are looking for a job in California, Colorado, or India, for other than that it has absolutely no product or company information. The Register reported in 2006 that former Transmeta CEO Matt Perry assumed the CEO position at Montalvo during that year. However, the News.com article yields several new insights, such as the fact that Peter Song, who previously founded MemoryLogix, is Montalvo’s chief architect, and that Peter Glaskowsky is their chief system architect. The company has so far raised $73 million through several venture capital firms. The currently published patent applications do not reveal much about the processor as they are focused mainly on power conservation via a buffer/mini-cache that either reduces DRAM accesses or provides information when the processor is in a low-power state and thus not available. The two patent applications can be found here and here. I was hoping of finding one of the Montalvo guys at the ISSCC conference this week in hope of obtaining some additional information; however, with thousands of engineers running around this proved to be a futile attempt. As such, unless Montalvo makes a public announcement later this year or emerges from stealth mode, it will be hard to make any comparisons to Transmeta or to assess the company’s chances.