Based out of Netanya, Israel Plurality has been working on multi-core designs since 2004. In 2007, the company offered a proof of concept chip that incorporated 16 32-bit RISC cores, and offered it to customers as an evaluation and development kit. Then, the company was supposed to follow this up with a 64-core 90nm commercial chip in Q3 of 2007. But unless I’ve missed the announcement, this commercial product seems to have never materialized. Maybe the company encountered some problems with the initial design, or maybe the 64 cores were simply a few too many to make the product cost effective in 90nm? - We will probably never find out.

Regardless, in February of this year Plurality announced that research has been completed on their HyperCore Architecture Line (HAL) of multi-core processors and hinted at an investment round that would finance the commercialization of a 256-core chip, now slated to hit the market some time in 2009. This round of financing occurred in July, and netted the company a nice $8m in funding. Other than the increased number of cores, not too much seems to have changed architecturally, at least on the high-level. The design still incorporates a hardware based synchronizer/scheduler that optimizes the load for each core, although the company hints at having filed several more patent applications which improve its performance. Additionally, the design continues to connect all the cores to a single shared memory, rather than allowing individual cores to have local caches.  Finally, the company is sticking by its task map programming model which requires the programmer to divide a particular algorithm into specific tasks that define dependencies. Plurality makes it sound as if this programming process is a piece of cake for a regular programmer, however, I would question whether a regular programmer can partition an algorithm efficiently into parallel tasks. Further, with this approach, quite a bit of work will be required to re-compile older programs for optimum performance - but that is generally the case anyhow. Optimally, Plurality should develop a compiler that would automatically generate a task map for their HyperCore processor; however, this has been tried many times before and is still very much the holy grail of parallel programming.

Last year we wrote about ionic wind engine research that was conducted at Purdue University and allowed the team to increase the heat-transfer coefficient of a regular fan by 250 percent, thus significantly improving the cooling solution. Since then chips have definitely not become any cooler. The power envelope for individual cores might have decreased due to the re-emergence of simpler architectures with shallower pipelines, but with chip companies squeezing ever more cores into smaller packages, the heat problem is not going away any time soon. To compound the problem, keep in mind that for all these cores to perform useful work, they need to constantly be supplied with data, which leads to more I/O circuitry. The I/O circuitry in turn often times consists of many analog blocks that generally don’t scale very well with voltage, leading to more heat.

But rest assured, where there are interesting problems to be sovled, smart minds somewhere are working on doing just that. As happens to be the case, once again researchers at Purdue University have developed a technology that through the use of microjets enables them to deposit liquid into tiny channels on the chip surface resulting in a high-performance cooling solution. Conventional chips generate about 100 watts per square centimeter and can be air cooled via heat sinks and fans. Liquid cooling solutions are generally limited to about 200 watts per square centimeter. The Purdue team claims that their new cooling technology will allow chips with a power density of up to 1,000 watts per square centimeter. The key for achieving this type of cooling is a non-conductive liquid called hydrofluorocarbon. This fluid is pumped into the tiny channels on the chip surface via microjets through holes in the metal plate that sits on top of the channels. As the liquid circulates through the channels, it heats up until it momentarily becomes a vapor, which significantly enhances the cooling process. The micorjets ensure that the fluid is evenly distributed along the channels. This avoids the previous pitfall of fluids traversing chips from one side to the other, heating up along the way and thus losing their cooling ability.

Of course, the question has to be asked whether it will be possible to commercialize this technology. In specific niches, such as super-computing, where cost usually takes a backseat to performance, this cooling solution might indeed be acceptable. However, unless the technology can be made affordable enough so that major chip vendors can incorporate it into their products without alienating their consumers, it will likely fall by the wayside. I don’t have any chip packaging background and as such estimating the costs of this approach in its present form are beyond me, however, something tells me that they are not insignificant.