Marseille Networks, based out of Silicon Valley, CA is claiming a lot with their latest press release, but only partially reveals its hand. The company claims to have reinvented the fabless semiconductor development process through what it refers to as a virtual tape-out methodology. These claims become even more stunning, when one considers that, as pointed out by VentureBeat’s Dean Takahashi, the company has a mere 20 employees and has raised a paltry, by semiconductor startup standards, $5 million in funding. Claims like these could be easily dismissed as wishful thinking on part of the company’s founders, but Marseille’s introduction of a complete line of Quad-HD (2160p – 3840 x 2160) video processors for the flat-panel TV, PC, and A/V markets makes this a bit difficult. Especially, since the company maintains that these complex chips were developed in less than 12 months. As part of the company’s Video Through Virtualization (VTV) 1200 family of processor, these chips have native Quad-HD support and also perform up-scaling of legacy HD content to Quad-HD. From the company’s press release it is not clear if a demo utilizing these new processors was performed at CES this year. Maybe someone who stopped by Marseille’s booth at CES could comment on this?

And while specifications and block diagrams are available for the VTV-1200 family of processors on Marseille’s website and are generally self-explanatory, how exactly the virtual tape-out methodology works is significantly less clear. According to the company, the VTV platform which enables the virtual tape-out flow is a hybrid hardware emulation and software simulation environment which sits on-top of Marseille’s proprietary switch fabric. The VTV platform consists of four major components: Tools, Hardware, Libraries, and Methodology. The info on the company’s web-site seems to indicate that the hardware is FPGA based. The key benefit, as shown in the picture above, seems to stem from the customer’s ability to start developing their software before the final chip is delivered, which in turn the company suggest should save anywhere between 6 – 12 months in design time. Based on this I fail to see how this is really a reinvention of the fabless development process. There are plenty of companies in the chip industry that provide software based simulators and FPGA based emulators to customers way before they deliver the final silicon. Of course, there might be more to the virtual tape-out flow than might appear at first. Are customers allowed to modify the architecture, integrate custom IP, and then re-program the FPGA continuously to analyze the changes in performance? Are the changes then communicated back to Marseille’s to be integrated into the final IC? Maybe, but as stated before, it is not exactly clear from the information that Marseille’s has published so far.

It’s been a while since we’ve had a chance to look through some of the research that the Kauffman Foundation has conducted recently, which is a real shame since these guys do indeed publish some very interesting reports. Back in 2007, we reviewed a rather lengthy report titled “On the Road to an Entrepreneurial Economy” which focused on policies the government should institute to promote innovative entrepreneurship. With the holiday season here and news on the semiconductor startup front rather on the slow side, we came across a rather short but relevant report that focuses on future job creation. Titled “Where Will the Jobs Come From?” this report examines the job creation patterns using the United Stated Census Bureau data from the last few years. The report contains a myriad of charts showing job creation vs. company age, job creation vs. company size, job creation vs. industry sector and so on, but the overall findings can be summarized in a single sentence: While large companies are important since they are part of a complex economic system in which the acquisitions they fund are essential exit strategies for a lot of startup companies, it is the actual startups which especially early on in their life cycle have been the major job creation engine in the United States. As such, policy makers ought to places most emphasis on enabling entrepreneurs in creating these young firms. The above is clearly somewhat of an oversimplification of the findings, but as noted previously, this report is rather on the short side and can be easily read over a cup of joe.

The reports reiterating a VC winter for semiconductor startups just keep on coming, the latest one being from Gartner, discussed here. And yet, clever startups keep on beating the odds, by obtaining funding even given all this negative press. The latest of which is Arteris, an EDA startup specializing in providing SoC interconnect IP and tools, based on the company’s Network-on-Chip (NoC) architecture. Founded in 2003, with headquarters in San Jose, CA and an engineering design center in Paris, France, Arteris just completed a strategic investment round that netted the company $9.7 million in funding. The funding round was led by Qualcomm and ARM, who joined an impressive list of investors including Synopsys, DoCoMo Capital, Crescendo Ventures, TVM Capital and Ventech, in making it possible. Arteris’ technology supports ARM’s Advanced Microcontroller Bus Architecture (AMBA) out of the box, but according to the company can be easily extended to support proprietary bus protocols.

The idea for NoC, the company admits, was taken from applicable concepts in the computer network arena and then adapted to IC design. Arteris currently offers three separate tool chains, depending on the design complexity at hand: FlexWay, FlexNoC, and NoC Solution. FlexWay is targeted to enable designers to quickly replace their current Advanced High-Performance Bus (AHB) by offering improved performance, support for heterogeneous interfaces, and a verification engine to verify the interconnects and interface protocol coverage. FlexNoC, as the next step up, offers multi-protocol support, is optimized for high-throughput while minimizing area and power, and also offers a test suite that promises a 100% interconnect coverage along with functional coverage test on the component interfaces. The top of the line tool, NoC Solution, is target at very complex designs and offers additional features such a Quality of Service (QoS) support, and multiple clock and power domain support, just to name a few. It also features a DRAM scheduler that integrates with the NoC architecture as needed. In addition to the verification engine mentioned beforehand, NoC Solution also comes with a NoCcompiler and NoCexplorer which allow designers to quickly capture, configure, and evaluate their bus architectures.

With the number of components that are being integrated onto SoCs increasing constantly, the tools that Arteris offers might indeed become essential. Especially for smaller integration teams that do not have the resources to evaluate and design proprietary bus architectures for their SoCs. I definitely think that Arteris is on the right track by focusing on a specific problem, namely the bus network architecture, an area which is only going to get more complicated in the near future.