When considering the consumer handheld market, one might not usually think of it as a segment that might be well served by a programmable device, such as a field-programmable gate array (FPGA). One reason being that FPGAs are usually produced using processes that are about a couple of generations behind the leading edge. This in turn makes these chips large and expensive, and thus not very suitable for markets were margins are razor thin. However, assuming that this problem can be overcome, suddenly FPGAs become a viable option, especially for applications that might require frequent upgrades due to ever changing standards. Enter SiliconBlue Technologies, a Sunnyvale, California based startup which claims to be the first company that has managed to combine non-volatile memory (NVM) and static RAM (SRAM) at the 65nm process node on a single chip. Unlike purely SRAM based FPGAs that require an external PROM to store the programming bit-stream, and have a configuration penalty, the SiliconBlue iCE family of devices can be turned on instantly. Additionally, since no bit-stream programming is necessary, there is also no danger of bit-stream snooping during the configuration process.  On the other hand, compared to purely NVM based devices, the iCE family is significantly smaller due to smaller SRAM geometries.

The current iCE 65nm family consists for four devices: iCE65L02, iCE65L04, iCE65L08, and iCE65L16, which contain from 1,792 to 15,260 logic cells. The current for the iCE chip family ranges from 25 to 250-uA at 32-KHz, and from 5 to 40-mA at 32MHz. The BGA packages for these devices range from 3x4 to 12x12 mm. Programming is performed in a similar manner to SRAM based FPGAs. The SiliconBlue chips are also available in DiCE packages to allow vendors to combine them with existing chips through multi-chip system-in-package (SiP) technology. Samples are available now and SiliconBlue also offers an iCEMAN evaluation board that features the iCE65L04 and iCECUBE development software.

The combination of NVM and SRAM definitely seems appealing, as well as the low-power consumption and package size. However, the FPGA space is a tough business and it is hard to tell whether SiliconBlue will flourish or fold. Many companies including Quicksilver, Adaptive Silicon, PlusLogic, and Chameleon, just to name a few, have tried taking on the industry big boys Altera and Xilinx, and have either failed or been absorbed. In SiliconBlue’s defense, the fact that company has been able to combine NVM and SRAM on a standard low-power CMOS process in 65nm, and claims to have a solid roadmap towards 45nm, might just give it the edge to stay ahead of the competition.

Earlier this week, WiSpry received an additional $7 million of Series B funding, brining the company’s total funding to $18 million so far. Based out of Irvine, California, WiSpry is a fabless semiconductor startup focused on the mobile communications market. In particular, the company has developed programmable radio frequency (RF) products which are made possible through the company’s patented integration technique of micro-electro-magnetic-systems (MEMS) devices with typical industry RF-CMOS flows. This in turn enables MEMS to be manufactured in regular IC foundries rather than in specific MEMS foundries as is done typically. For those not familiar with this technology, MEMS are microscopic devices that utilize moving parts to accomplish mechanical actions. Many companies utilize MEMS in their products, for example, TI the largest MEMS manufacturer in 2006 utilized them in their DLP chips, while Canon and HP utilized them in their printers. The real benefit of WiSpry’s approach is that it enables really tight integration of micro-electronics with micro-mechanical devices, effectively enabling complete system-on-a-chip solutions. According to the company, their process can be integrated with active silicon and is process agnostic, thus able to work with CMOS, SiGe, BiCMOS and GaAs. Currently, WiSpry’s product line is a family of RF-MEMS tunable digital capacitors that are offered in networked configurations. These capacitors operate similarly to regular parallel-plate capacitors, however the distance between the plates is tunable due to MEMS technology, and as such the capacitance can be varied. This product line is initially targeted at wireless devices for antenna tuning and filter applications. Further down the line WiSpry envisions the integration of their technology into transceivers, low-noise amplifiers and power amplifiers. The important part here is for the integration of the MEMS not to slow-down the production of the rest of the ICs significantly, or else it might become more cost effective for companies to do the production of these two separately. However, if this challenge can be overcome and given the fact that the market for wireless devices which require ever tighter integration of components is still growing, the market opportunities for WiSpry seem lucrative.

Memory capacity is one of those things that developers seem to have an infinite appetite for. How programs worked in the old days with a few Kbytes of memory is almost a mystery, but then again the type of information that is being crammed into memory for the sake of performance today is significantly different than even a decades ago. Yet, one has to wonder if programmers have gotten a ted lazy after trading in assembly skills for compiler optimizations. Regardless, MetaRAM, a two year old startup out of San Jose, California that emerged from stealth-mode a week ago is poised to make many new friends with their recent announcement of being able to quadruple the DRAM capacity of existing systems using existing DIMMs. Backed by several prominent venture capital firms including Kleiner Perkins Caulfield & Byers, Khosla Ventures, Storm Ventures, and Intel Capital, and led by Fred Weber who led the development of the Opteron processor at AMD, MetaRAM developed what they call MetaSDRAM technology.

As shown above, MetaRAM’s trick is a chipset that sits between the system memory controller and the actual DRAM. This chipset, which consists of an access manager chip, either the AM150 or AM160, and several flow controller chips, FC540, enables support for up to 16GB DIMMs without the need for any other hardware or software changes within the system. These chips work in tandem at speeds of up to 667 MT/s while being transparent to the host memory controller as well as the DRAMs.  This is definitely a clever trick, and as long as it does not inhibit the operating frequency it is a great way for upgrading current systems without having to re-work any additional hardware. Two questions emerge however that the company will have to address in the future: First, as the operating frequency of DRAMs increases, how long will MetaRAM be able to hide the latency of their chipset via clever buffering of reads and writes? Second, it is inevitable that memory controllers in the future will enable support for ever larger amounts of memory, is it possible therefore that at some point the amount of memory on a memory module will simply be limited by the physical integration limit, rather than by the controller capability? But for now things seem to be well at MetaRAM; several vendors have announced products based on MetaRAM’s chipsets and the company has also several open positions for those looking for something new to work on. If you want to find out a little bit more about the company’s co-founder and CEO head on over to The Register, where you can find a very interesting interview with Fred Weber which covers his career from the early days at Harvard, through NextGen, AMD, and finally MetaRAM.